In recent years, techniques such as clock gating and RAM macro chip enable control have been employed in semiconductor integrated circuit designs, aiming to reduce power consumption by disabling the portions of the circuit that are not in use and thereby suppressing unnecessary operation of the circuit.
However, when these techniques are applied to reduce power consumption, the difference between the maximum and minimum values of power that the circuit consumes increases, and as a result, the difference between the maximum and minimum values of the current that flows in the circuit also increases. This, for example, may result in increased power supply noise or may lead to malfunction of the circuit, posing a major obstacle to actively incorporating such power reduction techniques in semiconductor integrated circuit designs.
In a power supply system constructed from a die, package, and board, for example, if a current fluctuation (for example, a current fluctuation lower in frequency than about 100 MHz) occurs in a frequency band where the impedance is high, power supply noise increases.
One related art approach to suppressing such power supply noise has been to mount capacitors on the die (chip), package, or board so that the effect of power supply noise may be reduced below a permissible level even if a current fluctuation occurs.
As described above, in the related art, the effect of power supply noise has been be reduced below a permissible level in the event of a current fluctuation, for example, by mounting capacitors on the die, package, or board.
However, with this related art approach, as a lower voltage, larger current design becomes possible with further advances in miniaturization technology, the capacitance of the capacitors to suppress the power supply noise has to be increased, since ΔI/Δt (the amount of current fluctuation per unit time) increases.
This results in increased die size and increased cost due to an increase in the number of capacitors mounted on the package or board. On the other hand, if ΔI/Δt is reduced so as to be able to address the problem with a fewer number of capacitors by giving preference to the cost, limitations may be imposed on the power reduction techniques to be employed in semiconductor integrated circuit designs.
In the related art, various designs have been proposed for semiconductor integrated circuits including power supply noise suppression functions.
Patent document 1: Japanese Laid-open Patent Publication No. 2008-276612
Patent document 2: Japanese Laid-open Patent Publication No. 2009-099047